TroyTech International Consulting Pte Ltd (“TroyTech”) is a Singapore & APAC based consulting and professional services firm established in Singapore since Year 2000. We offers a wide range of services to our customers, from provision of professional recruitment solutions to various industry sectors (e.g. Semi-con industry, IT Industry, Insurance Industry, Telecommunication Industry, Transportation Industry, etc.) to provision of the most current and complete IT Solutions (e.g. IOT Solution /Java Solution /Analytics Solution /Mobile Solution /Big Data Solution /Test Solution /Modernization Solution/ Migration Solution), business integration consulting services and IBM software solutions consulting services. TroyTech is also an Asia Software Solution Center for software with distributorship for solutions from Singapore, Canada, Spain, USA, Netherlands, Japan, Taiwan, India. Besides Singapore, we have also established local presence in both Taiwan and Japan.
TroyTech International Consulting Pte Ltd
Company Registration No. 200001383M
EA License No.: 16C7920
Custom Layout Engineer | or | Physical Verification CAD Engineer (2 or more positions)
jobsDB Ref. JSG400003003035113
EA License No 16C7920
We are looking for result-driven candidates who can thrive under a fast-pace working environment and possess a strong desire to create an impact in the organization.
Job Position: Custom Layout Engineer
- Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
- Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
- Work closely with multi-functional teams to constantly optimize layout implementation for better power, performance, area and schedule
- Responsible for in-house RF/Analog projects and IP/library developments
- Bachelor’s degree in Electrical/Electronic/Computer Engineering
- Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in DRC/LVS debugging
- Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integration flow
- Have a good grasp of DRM of advanced node CMOS technologies
- Team player and effective in cross-team communication and time management
- Proficiency in script programming (eg. Tcl, Perl or C-shell) is a plus
- Experienced candidate will be considered for senior position
Job Position: Physical Verification CAD Engineer
- Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
- Co-work with Place & Route team to resolve full-chip layout integration issues.
- Coordinates with internal IP owners on IP related issues.
- Coordinates with Manufacturing Team on DRC related issues.
- Provide automation solutions to improve efficiency in tape-out flow.
- Report on tapeout issues.
- Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule deck for various processes
- Develop layout implementation flow and physical verification flow
- Co-work with QA team to reduce the PDKs/Rule deck defects
- Implement automation scripts in C-shell and Perl
- Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
- Familiar with IC Design front-to-backend flow
- Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
- Proficient in script programming, such as, Tcl, Perl or C-shell
- Proficient in UNIX (Linux) platforms
- Strong communication skills, problem solving and analytical skills